This invention relates to a binary data counting device used in a process, such as a Hough transform, for area sampling or line sampling in a pattern recognition device or the like of FA (Factory Automation) equipment, in particular to an area information sampling device or a Hough transform device which are application devices of the binary data counting device.
In the above described process of area sampling, a binary data counting device is used for the process of counting the number of xe2x80x9c1sxe2x80x9d in the binary image in order to sample the area of the xe2x80x9c1sxe2x80x9d (for example, black) region in a binary image (for example, the background is xe2x80x9c0xe2x80x9d (for example, white)).
It also is used, in the process of Hough transform, in a process of counting the number of xe2x80x9c1sxe2x80x9d (for example, black) which exist in a particular Japanese hand drum shaped region in a binary image (for example, the background is xe2x80x9c0xe2x80x9d (for example, white)).
Conventionally there are two major methods of counting the number of xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d in the data expressed in a binary manner comprising N (N is an integer of 2 or more) bits so as to take out the counting result as multi-valued data. Here, the data expressed in a binary manner comprising N bits can also be expressed as binary data of N bit length.
One is the method where data are set in a register of N bits, 1 bit is shifted to the left at an ALU (Arithmetic and Logic Unit), the value of the bit of the MSB (Most Significant Bit) is set for carrying and, in the case when the value is the desired value, the value of the accumulator is incremented by 1. This method can be implemented easily with software for the MCU (Micro Controller Unit) or the DSP (Digital Signal Processor).
That requires three instructions for the processing of 1 bit, however, which has defect that the processing speed is slow. In practical image processing, the processing object tends to be large, for example, 10,000 pixels by 10,000 pixels and, therefore, it is desirable that at least N bits are processed for one instruction implementation period. Accordingly, there is a method of using a dedicated circuit of hardware as another means.
An example of the method for implementation with hardware is described with reference to FIG. 6. FIG. 6 shows, in the case of N=16, a configuration of the case where the number of xe2x80x9c1sxe2x80x9d is counted. First, with respect to data BDATA 15 to BDATA 0, which are expressed in a binary manner and comprise 16 bits, every neighboring two bits are paired from the side of the LSB (Least Significant Bit) to make eight pairs in total. Then, those eight pairs are inputted into eight 1-bit adders AD18 to AD11, respectively, to perform the addition. As a result of this eight pieces of 2-bit data are formed.
Next, in the same way as above, with respect to eight pieces of 2-bit data outputted, respectively, from the 1-bit adders AD18 to AD11, every neighboring two pieces are paired from the side of the LSB to make four pairs in total. Then, those four pairs are inputted, respectively, into four 2-bit adders AD24 to AD21 to perform the addition. As a result of this four pieces of 3-bit data are formed.
Next, in the same way as the above, with respect to four pieces of 3-bit data outputted, respectively, from the 2-bit adders AD24 to AD21, every neighboring two pieces are paired from the side of the LSB to make two pairs in total. Then, those two pairs are, respectively, inputted into the two 3-bit adders AD32 and AD31 to perform the addition. As a result of this two pieces of 4-bit data are formed.
Next, those two pieces of 4-bit data are inputted into the 4-bit adder AD41 to perform the addition. As a result of this one piece of 5-bit data which corresponds to the number of xe2x80x9c1sxe2x80x9d in the data expressed in a binary system comprising sixteen bits is formed. That is to say, multi-valuing of the data expressed in a binary manner comprising sixteen bits is completed.
As described above, a counting device can be implemented by forming a network of adders.
On the contrary, in the case of N=16, fifteen adders in total are necessary, which are: 1-bit adderxc3x9716/2+2-bit adderxc3x9716/4+3-bit adderxc3x9716/8+4-bit adderxc3x9716/16. In addition, in the case of N=32, thirty one adders in total are necessary, which are: 1-bit adderxc3x9732/2+2-bit adderxc3x9732/4+3-bit adderxc3x9732/8+4-bit adderxc3x9732/16+5-bit adderxc3x9732/32. Accordingly, as hardware, not only the number of adders is enormous but also each of the adders themselves becomes complicated in the circuit configuration as the bit number increases, which leads to a large scale circuit as a whole.
As described in the above conventional examples there are the defects that though the former has a smaller circuit scale the process speed is too slow to be practical and though the latter is fast in the process speed compared to the former the circuit scale becomes large.
The purpose of the present invention is to provide a binary data counting device, an area information sampling device and a Hough transform device of which the processing speed is high and which can be implemented with a small circuit scale and at low cost.
A binary data counting device according to the first aspect of the invention counts the number of either one of the binary digit in the data expressed in a binary manner comprising N bits, which is provided with a shifter array for outputting the binary data of N bits. The shifter array comprises Nxc3x97(N+1)/2 shifters of which the control input is each bit value of the data expressed in a binary manner comprising N bits.
Nxc3x97(N+1)/2 shifters are mutually connected so that the binary data of N bits are outputted under the condition where one of the binary digits is filled in from one side in the same number as either one of the binary digits in the data expressed in a binary manner comprising N bits by controlling the operation of each shifter making up the shifter array with each bit value of the data expressed in a binary manner comprising N bits.
According to this configuration, the number of either one of the binary digits in the data expressed in a binary manner comprising N bits is counted and in the case of transform to a multi-valued numerical expression such as a decimal number or a hexadecimal number, the number of either one of the binary digits in the data expressed in a binary manner comprising N bits is not counted through a direct operation but the counting process of the binary data is implemented as in the following. That is to say, the binary data of N bits are outputted under the condition where the same number of one of the binary digits as the number of either one of the binary digits in the data expressed in a binary manner comprising N bits is filled in from one side by controlling the operation of each shifter making up the shifter array with each bit value of the data expressed in a binary manner comprising N bits.
That is to say, the process of counting the number of xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d in the data expressed in a binary manner comprising N bits is implemented by expressing binary data when filled in from, for example, the right side so as to be able to intentionally encode the number of xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d which are desired to be counted in the data expressed in a binary manner comprising N bits. In this case, it is possible that the operation of the shifter array can be completed with one clock and the circuit scale is much smaller in comparison to the adder. Accordingly, compared to a conventional example, the process of counting the number of xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d in the data expressed in a binary manner can be implemented with the processing speed being higher and the circuit scale being smaller so that an inexpensive binary data counting device can be provided. In addition, it is possible that the shift operation can be performed in a shorter span of time compared to the process of a multi-bit addition operation and, therefore, a process of higher speed than that of the circuit configuration by the network configuration of the adders becomes possible.
In the configuration of the above described first aspect of the invention, an encoder maybe provided which converts binary data outputted from the shifter array under the condition where one of the binary digits is filled in from one side to a multi-valued number in accordance with the position of one of the binary digits on the side of the MSB.
According to this configuration, the same effects as the configuration of the above described first aspect of the invention can be gained since the process of counting the number of either one of the binary digits in the data expressed in a binary manner comprising N bits is implemented by multi-valuing the binary data outputted from the shifter array in accordance with the position of either one of the binary digits on the side of the MSB by using the encoder.
In the configuration of the above described first aspect of the invention, a selection means can be provided for selectively designating either one of the binary digits in the data expressed in a binary manner comprising N bits for counting.
According to this configuration, the same effects as the configuration of the above described first aspect of the invention can be gained.
A binary data counting device according to the second aspect of the invention is to count the number of either one of the binary digits in the data expressed in a binary manner comprising N bits, which is provided with N bits flip-flop and a shifter array.
The N flip-flops have each bit value of the data expressed in a binary manner comprising N bits as respective input.
In the shifter array, Nxc3x97(N+1)/2 shifters with two inputs and one output are arranged in a triangle shape of N rows with a diagonal part of the arrangement in an Nxc3x97N matrix as an oblique side and with two side parts arranged in a matrix shape as the base and a perpendicular side, respectively, each of the outputs of the N flip-flops are control signals of the shifter for each row comprising the triangle shape and the output of the N shifters in the Nth row arranged on the base of the triangle shape are outputted as a binary data of N bits.
Then, when two inputs of the shifter are assumed as the first and the second inputs, whether the first input is outputted or the second input is outputted is selected as the output of the shifter by the control signal. One of the binary values is inputted to the first input of the shifter arranged on the oblique side part in the triangle shape and the output of the shifter belonging to the oblique side part of the front row is inputted into the second inputs of the shifters from the second row to the Nth row of the oblique side part. The other binary value is inputted into the second input of the shifter arranged along the perpendicular part of the triangle shape and the output of the shifter belonging to the vertical side part at the front row is inputted into the first inputs of the shifters from the second row to the Nth row of the perpendicular side parts. In addition, the output of the shifter in the same column of the front row is inputted into the first input of the shifter arranged in other areas than the oblique side part or the perpendicular side part of the triangle shape, and the output of the shifter arranged on the perpendicular side next to the shifter of the same column at the front row is inputted into the second input.
According to this configuration, the same effects as the configuration of the above described first aspect of the invention can be gained.
In the configuration of the above described second aspect of the invention, an encoder may be provided which converts the binary data of N bits outputted from the shifter array into a value gained by counting the number of either one of the binary digits of the data expressed in a binary manner.
According to this configuration, the same effects as the above described first aspect of the invention can be gained.
In the configuration of the above described second aspect of the invention, a selection means can also be provided which selectively designates either one of the binary digits in the data expressed in a binary manner comprising N bits for counting by switching between the conditions where the outputs of the N flip-flops are used without inversion as control signals of the shifter and the condition where the outputs of N flip-flops are inverted to be used as the control signal of the shifter.
According to this configuration, the same effects as the above described first aspect of the invention can be gained.
An area information sampling device according to the third aspect of the invention is the application of the binary data counting device according to the first aspect of the invention.
According to this configuration, the same effects as the binary data counting device according to the first aspect of the invention can be gained.
A Hough transform device according to the fourth aspect of the invention is the application of the binary data counting device according to the first aspect of the invention.
According to this configuration, the same effects as the binary data counting device according to the first aspect of the invention can be gained.